// $Module: reg_ive_top $
// $RegisterBank Version: V 1.0.00 $
// $Author:  $
// $Date: Wed, 05 Jan 2022 03:04:40 PM $
//

//GEN REG ADDR/OFFSET/MASK
#define  IVE_TOP_REG_0  0x0
#define  IVE_TOP_REG_1  0x4
#define  IVE_TOP_REG_2  0x8
#define  IVE_TOP_REG_3  0xc
#define  IVE_TOP_REG_H10  0x10
#define  IVE_TOP_REG_11  0x14
#define  IVE_TOP_REG_12  0x18
#define  IVE_TOP_REG_CSC_COEFF_0  0x1c
#define  IVE_TOP_REG_CSC_COEFF_1  0x20
#define  IVE_TOP_REG_CSC_COEFF_2  0x24
#define  IVE_TOP_REG_CSC_COEFF_3  0x28
#define  IVE_TOP_REG_CSC_COEFF_4  0x2c
#define  IVE_TOP_REG_CSC_COEFF_5  0x30
#define  IVE_TOP_REG_CSC_COEFF_6  0x34
#define  IVE_TOP_REG_CSC_COEFF_7  0x38
#define  IVE_TOP_REG_CSC_COEFF_8  0x3c
#define  IVE_TOP_REG_CSC_COEFF_9  0x40
#define  IVE_TOP_REG_CSC_COEFF_A  0x44
#define  IVE_TOP_REG_CSC_COEFF_B  0x48
#define  IVE_TOP_REG_14  0x4c
#define  IVE_TOP_REG_15  0x50
#define  IVE_TOP_REG_H54  0x54
#define  IVE_TOP_REG_H58  0x58
#define  IVE_TOP_REG_16  0x60
#define  IVE_TOP_REG_H64  0x64
#define  IVE_TOP_REG_H68  0x68
#define  IVE_TOP_REG_H6C  0x6c
#define  IVE_TOP_REG_H70  0x70
#define  IVE_TOP_REG_H74  0x74
#define  IVE_TOP_REG_20  0x78
#define  IVE_TOP_REG_21  0x7c
#define  IVE_TOP_REG_H80  0x80
#define  IVE_TOP_REG_84  0x84
#define  IVE_TOP_REG_90  0x90
#define  IVE_TOP_REG_94  0x94
#define  IVE_TOP_REG_98  0x98
#define  IVE_TOP_REG_RS_SRC_SIZE  0x100
#define  IVE_TOP_REG_RS_DST_SIZE  0x104
#define  IVE_TOP_REG_RS_H_SC  0x108
#define  IVE_TOP_REG_RS_V_SC  0x10c
#define  IVE_TOP_REG_RS_PH_INI  0x110
#define  IVE_TOP_REG_RS_NOR  0x114
#define  IVE_TOP_REG_RS_CTRL  0x118
#define  IVE_TOP_REG_RS_DBG_H1  0x11c
#define  IVE_TOP_REG_RS_DBG_H2  0x120
#define  IVE_TOP_REG_RS_DBG_V1  0x124
#define  IVE_TOP_REG_RS_DBG_V2  0x128
#define  IVE_TOP_REG_H130  0x130
#define  IVE_TOP_REG_H134  0x134
#define  IVE_TOP_REG_H138  0x138
#define  IVE_TOP_REG_H13C  0x13c
#define  IVE_TOP_REG_H140  0x140
#define  IVE_TOP_REG_H144  0x144
#define  IVE_TOP_REG_H148  0x148
#define  IVE_TOP_REG_H14C  0x14c
#define  IVE_TOP_REG_H150  0x150
#define  IVE_TOP_REG_H160  0x160
#define  IVE_TOP_REG_H164  0x164
#define  IVE_TOP_REG_H168  0x168
#define  IVE_TOP_REG_H16C  0x16c
#define  IVE_TOP_REG_H170  0x170
#define  IVE_TOP_REG_H174  0x174
#define  IVE_TOP_REG_R2Y4_11  0x180
#define  IVE_TOP_REG_R2Y4_12  0x184
#define  IVE_TOP_REG_R2Y4_COEFF_0  0x188
#define  IVE_TOP_REG_R2Y4_COEFF_1  0x18c
#define  IVE_TOP_REG_R2Y4_COEFF_2  0x190
#define  IVE_TOP_REG_R2Y4_COEFF_3  0x194
#define  IVE_TOP_REG_R2Y4_COEFF_4  0x198
#define  IVE_TOP_REG_R2Y4_COEFF_5  0x19c
#define  IVE_TOP_REG_R2Y4_COEFF_6  0x1a0
#define  IVE_TOP_REG_R2Y4_COEFF_7  0x1a4
#define  IVE_TOP_REG_R2Y4_COEFF_8  0x1a8
#define  IVE_TOP_REG_R2Y4_COEFF_9  0x1ac
#define  IVE_TOP_REG_R2Y4_COEFF_A  0x1b0
#define  IVE_TOP_REG_R2Y4_COEFF_B  0x1b4
#define  IVE_TOP_REG_R2Y4_14  0x1bc
#define  IVE_TOP_REG_IMG_IN_UV_SWAP   0x0
#define  IVE_TOP_REG_IMG_IN_UV_SWAP_OFFSET 0
#define  IVE_TOP_REG_IMG_IN_UV_SWAP_MASK   0x1
#define  IVE_TOP_REG_IMG_IN_UV_SWAP_BITS   0x1
#define  IVE_TOP_REG_IMG_1_UV_SWAP   0x0
#define  IVE_TOP_REG_IMG_1_UV_SWAP_OFFSET 1
#define  IVE_TOP_REG_IMG_1_UV_SWAP_MASK   0x2
#define  IVE_TOP_REG_IMG_1_UV_SWAP_BITS   0x1
#define  IVE_TOP_REG_RDMA_EIGVAL_UV_SWAP   0x0
#define  IVE_TOP_REG_RDMA_EIGVAL_UV_SWAP_OFFSET 2
#define  IVE_TOP_REG_RDMA_EIGVAL_UV_SWAP_MASK   0x4
#define  IVE_TOP_REG_RDMA_EIGVAL_UV_SWAP_BITS   0x1
#define  IVE_TOP_REG_TRIG_CNT   0x0
#define  IVE_TOP_REG_TRIG_CNT_OFFSET 4
#define  IVE_TOP_REG_TRIG_CNT_MASK   0xf0
#define  IVE_TOP_REG_TRIG_CNT_BITS   0x4
#define  IVE_TOP_REG_SOFTRST   0x4
#define  IVE_TOP_REG_SOFTRST_OFFSET 0
#define  IVE_TOP_REG_SOFTRST_MASK   0x1
#define  IVE_TOP_REG_SOFTRST_BITS   0x1
#define  IVE_TOP_REG_SHDW_SEL   0x4
#define  IVE_TOP_REG_SHDW_SEL_OFFSET 1
#define  IVE_TOP_REG_SHDW_SEL_MASK   0x2
#define  IVE_TOP_REG_SHDW_SEL_BITS   0x1
#define  IVE_TOP_REG_FMT_VLD_FG   0x4
#define  IVE_TOP_REG_FMT_VLD_FG_OFFSET 4
#define  IVE_TOP_REG_FMT_VLD_FG_MASK   0x10
#define  IVE_TOP_REG_FMT_VLD_FG_BITS   0x1
#define  IVE_TOP_REG_FMT_VLD_CCL   0x4
#define  IVE_TOP_REG_FMT_VLD_CCL_OFFSET 5
#define  IVE_TOP_REG_FMT_VLD_CCL_MASK   0x20
#define  IVE_TOP_REG_FMT_VLD_CCL_BITS   0x1
#define  IVE_TOP_REG_FMT_VLD_DMAF   0x4
#define  IVE_TOP_REG_FMT_VLD_DMAF_OFFSET 6
#define  IVE_TOP_REG_FMT_VLD_DMAF_MASK   0x40
#define  IVE_TOP_REG_FMT_VLD_DMAF_BITS   0x1
#define  IVE_TOP_REG_FMT_VLD_LK   0x4
#define  IVE_TOP_REG_FMT_VLD_LK_OFFSET 7
#define  IVE_TOP_REG_FMT_VLD_LK_MASK   0x80
#define  IVE_TOP_REG_FMT_VLD_LK_BITS   0x1
#define  IVE_TOP_REG_CMDQ_TSK_TRIG   0x4
#define  IVE_TOP_REG_CMDQ_TSK_TRIG_OFFSET 8
#define  IVE_TOP_REG_CMDQ_TSK_TRIG_MASK   0x1f00
#define  IVE_TOP_REG_CMDQ_TSK_TRIG_BITS   0x5
#define  IVE_TOP_REG_CMDQ_TSK_SEL   0x4
#define  IVE_TOP_REG_CMDQ_TSK_SEL_OFFSET 16
#define  IVE_TOP_REG_CMDQ_TSK_SEL_MASK   0x10000
#define  IVE_TOP_REG_CMDQ_TSK_SEL_BITS   0x1
#define  IVE_TOP_REG_CMDQ_TSK_EN   0x4
#define  IVE_TOP_REG_CMDQ_TSK_EN_OFFSET 17
#define  IVE_TOP_REG_CMDQ_TSK_EN_MASK   0x20000
#define  IVE_TOP_REG_CMDQ_TSK_EN_BITS   0x1
#define  IVE_TOP_REG_DMA_ABORT   0x4
#define  IVE_TOP_REG_DMA_ABORT_OFFSET 18
#define  IVE_TOP_REG_DMA_ABORT_MASK   0x40000
#define  IVE_TOP_REG_DMA_ABORT_BITS   0x1
#define  IVE_TOP_REG_WDMA_ABORT_DONE   0x4
#define  IVE_TOP_REG_WDMA_ABORT_DONE_OFFSET 19
#define  IVE_TOP_REG_WDMA_ABORT_DONE_MASK   0x80000
#define  IVE_TOP_REG_WDMA_ABORT_DONE_BITS   0x1
#define  IVE_TOP_REG_RDMA_ABORT_DONE   0x4
#define  IVE_TOP_REG_RDMA_ABORT_DONE_OFFSET 20
#define  IVE_TOP_REG_RDMA_ABORT_DONE_MASK   0x100000
#define  IVE_TOP_REG_RDMA_ABORT_DONE_BITS   0x1
#define  IVE_TOP_REG_IMG_IN_AXI_IDLE   0x4
#define  IVE_TOP_REG_IMG_IN_AXI_IDLE_OFFSET 21
#define  IVE_TOP_REG_IMG_IN_AXI_IDLE_MASK   0x200000
#define  IVE_TOP_REG_IMG_IN_AXI_IDLE_BITS   0x1
#define  IVE_TOP_REG_ODMA_AXI_IDLE   0x4
#define  IVE_TOP_REG_ODMA_AXI_IDLE_OFFSET 22
#define  IVE_TOP_REG_ODMA_AXI_IDLE_MASK   0x400000
#define  IVE_TOP_REG_ODMA_AXI_IDLE_BITS   0x1
#define  IVE_TOP_REG_IMG_WIDTHM1   0x8
#define  IVE_TOP_REG_IMG_WIDTHM1_OFFSET 0
#define  IVE_TOP_REG_IMG_WIDTHM1_MASK   0x1fff
#define  IVE_TOP_REG_IMG_WIDTHM1_BITS   0xd
#define  IVE_TOP_REG_IMG_HEIGHTM1   0x8
#define  IVE_TOP_REG_IMG_HEIGHTM1_OFFSET 16
#define  IVE_TOP_REG_IMG_HEIGHTM1_MASK   0x1fff0000
#define  IVE_TOP_REG_IMG_HEIGHTM1_BITS   0xd
#define  IVE_TOP_REG_IMGMUX_IMG0_SEL   0xc
#define  IVE_TOP_REG_IMGMUX_IMG0_SEL_OFFSET 0
#define  IVE_TOP_REG_IMGMUX_IMG0_SEL_MASK   0x1
#define  IVE_TOP_REG_IMGMUX_IMG0_SEL_BITS   0x1
#define  IVE_TOP_REG_MAPMUX_RDMA_SEL   0xc
#define  IVE_TOP_REG_MAPMUX_RDMA_SEL_OFFSET 1
#define  IVE_TOP_REG_MAPMUX_RDMA_SEL_MASK   0x2
#define  IVE_TOP_REG_MAPMUX_RDMA_SEL_BITS   0x1
#define  IVE_TOP_REG_IVE_RDMA_IMG1_EN   0xc
#define  IVE_TOP_REG_IVE_RDMA_IMG1_EN_OFFSET 2
#define  IVE_TOP_REG_IVE_RDMA_IMG1_EN_MASK   0x4
#define  IVE_TOP_REG_IVE_RDMA_IMG1_EN_BITS   0x1
#define  IVE_TOP_REG_IVE_RDMA_IMG1_MOD_U8   0xc
#define  IVE_TOP_REG_IVE_RDMA_IMG1_MOD_U8_OFFSET 3
#define  IVE_TOP_REG_IVE_RDMA_IMG1_MOD_U8_MASK   0x8
#define  IVE_TOP_REG_IVE_RDMA_IMG1_MOD_U8_BITS   0x1
#define  IVE_TOP_REG_IVE_RDMA_EIGVAL_EN   0xc
#define  IVE_TOP_REG_IVE_RDMA_EIGVAL_EN_OFFSET 4
#define  IVE_TOP_REG_IVE_RDMA_EIGVAL_EN_MASK   0x10
#define  IVE_TOP_REG_IVE_RDMA_EIGVAL_EN_BITS   0x1
#define  IVE_TOP_REG_MUXSEL_GRADFG   0xc
#define  IVE_TOP_REG_MUXSEL_GRADFG_OFFSET 5
#define  IVE_TOP_REG_MUXSEL_GRADFG_MASK   0x20
#define  IVE_TOP_REG_MUXSEL_GRADFG_BITS   0x1
#define  IVE_TOP_REG_DMA_SHARE_MUX_SELGMM   0xc
#define  IVE_TOP_REG_DMA_SHARE_MUX_SELGMM_OFFSET 6
#define  IVE_TOP_REG_DMA_SHARE_MUX_SELGMM_MASK   0x40
#define  IVE_TOP_REG_DMA_SHARE_MUX_SELGMM_BITS   0x1
#define  IVE_TOP_REG_IMG_IN_TOP_ENABLE   0x10
#define  IVE_TOP_REG_IMG_IN_TOP_ENABLE_OFFSET 0
#define  IVE_TOP_REG_IMG_IN_TOP_ENABLE_MASK   0x1
#define  IVE_TOP_REG_IMG_IN_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_RESIZE_TOP_ENABLE   0x10
#define  IVE_TOP_REG_RESIZE_TOP_ENABLE_OFFSET 1
#define  IVE_TOP_REG_RESIZE_TOP_ENABLE_MASK   0x2
#define  IVE_TOP_REG_RESIZE_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_GMM_TOP_ENABLE   0x10
#define  IVE_TOP_REG_GMM_TOP_ENABLE_OFFSET 2
#define  IVE_TOP_REG_GMM_TOP_ENABLE_MASK   0x4
#define  IVE_TOP_REG_GMM_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_CSC_TOP_ENABLE   0x10
#define  IVE_TOP_REG_CSC_TOP_ENABLE_OFFSET 3
#define  IVE_TOP_REG_CSC_TOP_ENABLE_MASK   0x8
#define  IVE_TOP_REG_CSC_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_RDMA_IMG1_TOP_ENABLE   0x10
#define  IVE_TOP_REG_RDMA_IMG1_TOP_ENABLE_OFFSET 4
#define  IVE_TOP_REG_RDMA_IMG1_TOP_ENABLE_MASK   0x10
#define  IVE_TOP_REG_RDMA_IMG1_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_BGM_TOP_ENABLE   0x10
#define  IVE_TOP_REG_BGM_TOP_ENABLE_OFFSET 5
#define  IVE_TOP_REG_BGM_TOP_ENABLE_MASK   0x20
#define  IVE_TOP_REG_BGM_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_BGU_TOP_ENABLE   0x10
#define  IVE_TOP_REG_BGU_TOP_ENABLE_OFFSET 6
#define  IVE_TOP_REG_BGU_TOP_ENABLE_MASK   0x40
#define  IVE_TOP_REG_BGU_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_R2Y4_TOP_ENABLE   0x10
#define  IVE_TOP_REG_R2Y4_TOP_ENABLE_OFFSET 7
#define  IVE_TOP_REG_R2Y4_TOP_ENABLE_MASK   0x80
#define  IVE_TOP_REG_R2Y4_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_MAP_TOP_ENABLE   0x10
#define  IVE_TOP_REG_MAP_TOP_ENABLE_OFFSET 8
#define  IVE_TOP_REG_MAP_TOP_ENABLE_MASK   0x100
#define  IVE_TOP_REG_MAP_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_RDMA_EIGVAL_TOP_ENABLE   0x10
#define  IVE_TOP_REG_RDMA_EIGVAL_TOP_ENABLE_OFFSET 9
#define  IVE_TOP_REG_RDMA_EIGVAL_TOP_ENABLE_MASK   0x200
#define  IVE_TOP_REG_RDMA_EIGVAL_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_THRESH_TOP_ENABLE   0x10
#define  IVE_TOP_REG_THRESH_TOP_ENABLE_OFFSET 10
#define  IVE_TOP_REG_THRESH_TOP_ENABLE_MASK   0x400
#define  IVE_TOP_REG_THRESH_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_HIST_TOP_ENABLE   0x10
#define  IVE_TOP_REG_HIST_TOP_ENABLE_OFFSET 11
#define  IVE_TOP_REG_HIST_TOP_ENABLE_MASK   0x800
#define  IVE_TOP_REG_HIST_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_INTG_TOP_ENABLE   0x10
#define  IVE_TOP_REG_INTG_TOP_ENABLE_OFFSET 12
#define  IVE_TOP_REG_INTG_TOP_ENABLE_MASK   0x1000
#define  IVE_TOP_REG_INTG_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_NCC_TOP_ENABLE   0x10
#define  IVE_TOP_REG_NCC_TOP_ENABLE_OFFSET 13
#define  IVE_TOP_REG_NCC_TOP_ENABLE_MASK   0x2000
#define  IVE_TOP_REG_NCC_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_SAD_TOP_ENABLE   0x10
#define  IVE_TOP_REG_SAD_TOP_ENABLE_OFFSET 14
#define  IVE_TOP_REG_SAD_TOP_ENABLE_MASK   0x4000
#define  IVE_TOP_REG_SAD_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_FILTEROP_TOP_ENABLE   0x10
#define  IVE_TOP_REG_FILTEROP_TOP_ENABLE_OFFSET 15
#define  IVE_TOP_REG_FILTEROP_TOP_ENABLE_MASK   0x8000
#define  IVE_TOP_REG_FILTEROP_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_DMAF_TOP_ENABLE   0x10
#define  IVE_TOP_REG_DMAF_TOP_ENABLE_OFFSET 16
#define  IVE_TOP_REG_DMAF_TOP_ENABLE_MASK   0x10000
#define  IVE_TOP_REG_DMAF_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_CCL_TOP_ENABLE   0x10
#define  IVE_TOP_REG_CCL_TOP_ENABLE_OFFSET 17
#define  IVE_TOP_REG_CCL_TOP_ENABLE_MASK   0x20000
#define  IVE_TOP_REG_CCL_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_LK_TOP_ENABLE   0x10
#define  IVE_TOP_REG_LK_TOP_ENABLE_OFFSET 18
#define  IVE_TOP_REG_LK_TOP_ENABLE_MASK   0x40000
#define  IVE_TOP_REG_LK_TOP_ENABLE_BITS   0x1
#define  IVE_TOP_REG_CSC_TAB_SW_0   0x14
#define  IVE_TOP_REG_CSC_TAB_SW_0_OFFSET 0
#define  IVE_TOP_REG_CSC_TAB_SW_0_MASK   0xfff
#define  IVE_TOP_REG_CSC_TAB_SW_0_BITS   0xc
#define  IVE_TOP_REG_CSC_TAB_SW_1   0x14
#define  IVE_TOP_REG_CSC_TAB_SW_1_OFFSET 16
#define  IVE_TOP_REG_CSC_TAB_SW_1_MASK   0x7fff0000
#define  IVE_TOP_REG_CSC_TAB_SW_1_BITS   0xf
#define  IVE_TOP_REG_CSC_TAB_SW_UPDATE   0x18
#define  IVE_TOP_REG_CSC_TAB_SW_UPDATE_OFFSET 0
#define  IVE_TOP_REG_CSC_TAB_SW_UPDATE_MASK   0x1
#define  IVE_TOP_REG_CSC_TAB_SW_UPDATE_BITS   0x1
#define  IVE_TOP_REG_CSC_COEFF_SW_UPDATE   0x18
#define  IVE_TOP_REG_CSC_COEFF_SW_UPDATE_OFFSET 16
#define  IVE_TOP_REG_CSC_COEFF_SW_UPDATE_MASK   0x10000
#define  IVE_TOP_REG_CSC_COEFF_SW_UPDATE_BITS   0x1
#define  IVE_TOP_REG_CSC_COEFF_SW_00   0x1c
#define  IVE_TOP_REG_CSC_COEFF_SW_00_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_00_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_00_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_01   0x20
#define  IVE_TOP_REG_CSC_COEFF_SW_01_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_01_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_01_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_02   0x24
#define  IVE_TOP_REG_CSC_COEFF_SW_02_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_02_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_02_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_03   0x28
#define  IVE_TOP_REG_CSC_COEFF_SW_03_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_03_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_03_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_04   0x2c
#define  IVE_TOP_REG_CSC_COEFF_SW_04_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_04_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_04_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_05   0x30
#define  IVE_TOP_REG_CSC_COEFF_SW_05_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_05_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_05_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_06   0x34
#define  IVE_TOP_REG_CSC_COEFF_SW_06_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_06_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_06_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_07   0x38
#define  IVE_TOP_REG_CSC_COEFF_SW_07_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_07_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_07_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_08   0x3c
#define  IVE_TOP_REG_CSC_COEFF_SW_08_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_08_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_08_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_09   0x40
#define  IVE_TOP_REG_CSC_COEFF_SW_09_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_09_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_09_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_10   0x44
#define  IVE_TOP_REG_CSC_COEFF_SW_10_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_10_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_10_BITS   0x13
#define  IVE_TOP_REG_CSC_COEFF_SW_11   0x48
#define  IVE_TOP_REG_CSC_COEFF_SW_11_OFFSET 0
#define  IVE_TOP_REG_CSC_COEFF_SW_11_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_COEFF_SW_11_BITS   0x13
#define  IVE_TOP_REG_CSC_ENMODE   0x4c
#define  IVE_TOP_REG_CSC_ENMODE_OFFSET 0
#define  IVE_TOP_REG_CSC_ENMODE_MASK   0xf
#define  IVE_TOP_REG_CSC_ENMODE_BITS   0x4
#define  IVE_TOP_REG_CSC_ENABLE   0x4c
#define  IVE_TOP_REG_CSC_ENABLE_OFFSET 4
#define  IVE_TOP_REG_CSC_ENABLE_MASK   0x10
#define  IVE_TOP_REG_CSC_ENABLE_BITS   0x1
#define  IVE_TOP_REG_LBP_U8BIT_THR   0x50
#define  IVE_TOP_REG_LBP_U8BIT_THR_OFFSET 0
#define  IVE_TOP_REG_LBP_U8BIT_THR_MASK   0xff
#define  IVE_TOP_REG_LBP_U8BIT_THR_BITS   0x8
#define  IVE_TOP_REG_LBP_S8BIT_THR   0x50
#define  IVE_TOP_REG_LBP_S8BIT_THR_OFFSET 8
#define  IVE_TOP_REG_LBP_S8BIT_THR_MASK   0xff00
#define  IVE_TOP_REG_LBP_S8BIT_THR_BITS   0x8
#define  IVE_TOP_REG_LBP_ENMODE   0x50
#define  IVE_TOP_REG_LBP_ENMODE_OFFSET 16
#define  IVE_TOP_REG_LBP_ENMODE_MASK   0x10000
#define  IVE_TOP_REG_LBP_ENMODE_BITS   0x1
#define  IVE_TOP_REG_IVE_DMA_IDLE   0x54
#define  IVE_TOP_REG_IVE_DMA_IDLE_OFFSET 0
#define  IVE_TOP_REG_IVE_DMA_IDLE_MASK   0xffffffff
#define  IVE_TOP_REG_IVE_DMA_IDLE_BITS   0x20
#define  IVE_TOP_REG_IVE_GMM_DMA_IDLE   0x58
#define  IVE_TOP_REG_IVE_GMM_DMA_IDLE_OFFSET 0
#define  IVE_TOP_REG_IVE_GMM_DMA_IDLE_MASK   0xffffffff
#define  IVE_TOP_REG_IVE_GMM_DMA_IDLE_BITS   0x20
#define  IVE_TOP_REG_DBG_EN   0x60
#define  IVE_TOP_REG_DBG_EN_OFFSET 0
#define  IVE_TOP_REG_DBG_EN_MASK   0x1
#define  IVE_TOP_REG_DBG_EN_BITS   0x1
#define  IVE_TOP_REG_DBG_SEL   0x60
#define  IVE_TOP_REG_DBG_SEL_OFFSET 4
#define  IVE_TOP_REG_DBG_SEL_MASK   0xf0
#define  IVE_TOP_REG_DBG_SEL_BITS   0x4
#define  IVE_TOP_REG_DBG_COL   0x64
#define  IVE_TOP_REG_DBG_COL_OFFSET 0
#define  IVE_TOP_REG_DBG_COL_MASK   0xffff
#define  IVE_TOP_REG_DBG_COL_BITS   0x10
#define  IVE_TOP_REG_DBG_ROW   0x64
#define  IVE_TOP_REG_DBG_ROW_OFFSET 16
#define  IVE_TOP_REG_DBG_ROW_MASK   0xffff0000
#define  IVE_TOP_REG_DBG_ROW_BITS   0x10
#define  IVE_TOP_REG_DBG_STATUS   0x68
#define  IVE_TOP_REG_DBG_STATUS_OFFSET 0
#define  IVE_TOP_REG_DBG_STATUS_MASK   0xffffffff
#define  IVE_TOP_REG_DBG_STATUS_BITS   0x20
#define  IVE_TOP_REG_DBG_PIX   0x6c
#define  IVE_TOP_REG_DBG_PIX_OFFSET 0
#define  IVE_TOP_REG_DBG_PIX_MASK   0xffff
#define  IVE_TOP_REG_DBG_PIX_BITS   0x10
#define  IVE_TOP_REG_DBG_LINE   0x6c
#define  IVE_TOP_REG_DBG_LINE_OFFSET 16
#define  IVE_TOP_REG_DBG_LINE_MASK   0xffff0000
#define  IVE_TOP_REG_DBG_LINE_BITS   0x10
#define  IVE_TOP_REG_DBG_DATA   0x70
#define  IVE_TOP_REG_DBG_DATA_OFFSET 0
#define  IVE_TOP_REG_DBG_DATA_MASK   0xffffffff
#define  IVE_TOP_REG_DBG_DATA_BITS   0x20
#define  IVE_TOP_REG_DBG_PERFMT   0x74
#define  IVE_TOP_REG_DBG_PERFMT_OFFSET 0
#define  IVE_TOP_REG_DBG_PERFMT_MASK   0x1
#define  IVE_TOP_REG_DBG_PERFMT_BITS   0x1
#define  IVE_TOP_REG_DBG_FMT   0x74
#define  IVE_TOP_REG_DBG_FMT_OFFSET 16
#define  IVE_TOP_REG_DBG_FMT_MASK   0xffff0000
#define  IVE_TOP_REG_DBG_FMT_BITS   0x10
#define  IVE_TOP_REG_FRAME2OP_OP_MODE   0x78
#define  IVE_TOP_REG_FRAME2OP_OP_MODE_OFFSET 0
#define  IVE_TOP_REG_FRAME2OP_OP_MODE_MASK   0x7
#define  IVE_TOP_REG_FRAME2OP_OP_MODE_BITS   0x3
#define  IVE_TOP_REG_FRAME2OP_SUB_MODE   0x78
#define  IVE_TOP_REG_FRAME2OP_SUB_MODE_OFFSET 3
#define  IVE_TOP_REG_FRAME2OP_SUB_MODE_MASK   0x8
#define  IVE_TOP_REG_FRAME2OP_SUB_MODE_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_SUB_CHANGE_ORDER   0x78
#define  IVE_TOP_REG_FRAME2OP_SUB_CHANGE_ORDER_OFFSET 4
#define  IVE_TOP_REG_FRAME2OP_SUB_CHANGE_ORDER_MASK   0x10
#define  IVE_TOP_REG_FRAME2OP_SUB_CHANGE_ORDER_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_ROUNDING   0x78
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_ROUNDING_OFFSET 5
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_ROUNDING_MASK   0x20
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_ROUNDING_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_CLIPPING   0x78
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_CLIPPING_OFFSET 6
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_CLIPPING_MASK   0x40
#define  IVE_TOP_REG_FRAME2OP_ADD_MODE_CLIPPING_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_SUB_SWITCH_SRC   0x78
#define  IVE_TOP_REG_FRAME2OP_SUB_SWITCH_SRC_OFFSET 7
#define  IVE_TOP_REG_FRAME2OP_SUB_SWITCH_SRC_MASK   0x80
#define  IVE_TOP_REG_FRAME2OP_SUB_SWITCH_SRC_BITS   0x1
#define  IVE_TOP_REG_FRAM2OP_X_U0Q16   0x7c
#define  IVE_TOP_REG_FRAM2OP_X_U0Q16_OFFSET 0
#define  IVE_TOP_REG_FRAM2OP_X_U0Q16_MASK   0xffff
#define  IVE_TOP_REG_FRAM2OP_X_U0Q16_BITS   0x10
#define  IVE_TOP_REG_FRAM2OP_Y_U0Q16   0x7c
#define  IVE_TOP_REG_FRAM2OP_Y_U0Q16_OFFSET 16
#define  IVE_TOP_REG_FRAM2OP_Y_U0Q16_MASK   0xffff0000
#define  IVE_TOP_REG_FRAM2OP_Y_U0Q16_BITS   0x10
#define  IVE_TOP_REG_FRAME2OP_FG_OP_MODE   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_OP_MODE_OFFSET 0
#define  IVE_TOP_REG_FRAME2OP_FG_OP_MODE_MASK   0x7
#define  IVE_TOP_REG_FRAME2OP_FG_OP_MODE_BITS   0x3
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_MODE   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_MODE_OFFSET 3
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_MODE_MASK   0x8
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_MODE_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_CHANGE_ORDER   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_CHANGE_ORDER_OFFSET 4
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_CHANGE_ORDER_MASK   0x10
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_CHANGE_ORDER_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_ROUNDING   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_ROUNDING_OFFSET 5
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_ROUNDING_MASK   0x20
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_ROUNDING_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_CLIPPING   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_CLIPPING_OFFSET 6
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_CLIPPING_MASK   0x40
#define  IVE_TOP_REG_FRAME2OP_FG_ADD_MODE_CLIPPING_BITS   0x1
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_SWITCH_SRC   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_SWITCH_SRC_OFFSET 7
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_SWITCH_SRC_MASK   0x80
#define  IVE_TOP_REG_FRAME2OP_FG_SUB_SWITCH_SRC_BITS   0x1
#define  IVE_TOP_REG_FRAM2OP_FG_X_U0Q16   0x84
#define  IVE_TOP_REG_FRAM2OP_FG_X_U0Q16_OFFSET 0
#define  IVE_TOP_REG_FRAM2OP_FG_X_U0Q16_MASK   0xffff
#define  IVE_TOP_REG_FRAM2OP_FG_X_U0Q16_BITS   0x10
#define  IVE_TOP_REG_FRAM2OP_FG_Y_U0Q16   0x84
#define  IVE_TOP_REG_FRAM2OP_FG_Y_U0Q16_OFFSET 16
#define  IVE_TOP_REG_FRAM2OP_FG_Y_U0Q16_MASK   0xffff0000
#define  IVE_TOP_REG_FRAM2OP_FG_Y_U0Q16_BITS   0x10
#define  IVE_TOP_REG_FRAME_DONE_IMG_IN   0x90
#define  IVE_TOP_REG_FRAME_DONE_IMG_IN_OFFSET 0
#define  IVE_TOP_REG_FRAME_DONE_IMG_IN_MASK   0x1
#define  IVE_TOP_REG_FRAME_DONE_IMG_IN_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_RDMA_IMG1   0x90
#define  IVE_TOP_REG_FRAME_DONE_RDMA_IMG1_OFFSET 1
#define  IVE_TOP_REG_FRAME_DONE_RDMA_IMG1_MASK   0x2
#define  IVE_TOP_REG_FRAME_DONE_RDMA_IMG1_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_RDMA_EIGVAL   0x90
#define  IVE_TOP_REG_FRAME_DONE_RDMA_EIGVAL_OFFSET 2
#define  IVE_TOP_REG_FRAME_DONE_RDMA_EIGVAL_MASK   0x4
#define  IVE_TOP_REG_FRAME_DONE_RDMA_EIGVAL_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_RESIZE   0x90
#define  IVE_TOP_REG_FRAME_DONE_RESIZE_OFFSET 3
#define  IVE_TOP_REG_FRAME_DONE_RESIZE_MASK   0x8
#define  IVE_TOP_REG_FRAME_DONE_RESIZE_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_GMM   0x90
#define  IVE_TOP_REG_FRAME_DONE_GMM_OFFSET 4
#define  IVE_TOP_REG_FRAME_DONE_GMM_MASK   0x10
#define  IVE_TOP_REG_FRAME_DONE_GMM_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_CSC   0x90
#define  IVE_TOP_REG_FRAME_DONE_CSC_OFFSET 5
#define  IVE_TOP_REG_FRAME_DONE_CSC_MASK   0x20
#define  IVE_TOP_REG_FRAME_DONE_CSC_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_HIST   0x90
#define  IVE_TOP_REG_FRAME_DONE_HIST_OFFSET 6
#define  IVE_TOP_REG_FRAME_DONE_HIST_MASK   0x40
#define  IVE_TOP_REG_FRAME_DONE_HIST_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_INTG   0x90
#define  IVE_TOP_REG_FRAME_DONE_INTG_OFFSET 7
#define  IVE_TOP_REG_FRAME_DONE_INTG_MASK   0x80
#define  IVE_TOP_REG_FRAME_DONE_INTG_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_SAD   0x90
#define  IVE_TOP_REG_FRAME_DONE_SAD_OFFSET 8
#define  IVE_TOP_REG_FRAME_DONE_SAD_MASK   0x100
#define  IVE_TOP_REG_FRAME_DONE_SAD_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_NCC   0x90
#define  IVE_TOP_REG_FRAME_DONE_NCC_OFFSET 9
#define  IVE_TOP_REG_FRAME_DONE_NCC_MASK   0x200
#define  IVE_TOP_REG_FRAME_DONE_NCC_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_BGM   0x90
#define  IVE_TOP_REG_FRAME_DONE_BGM_OFFSET 10
#define  IVE_TOP_REG_FRAME_DONE_BGM_MASK   0x400
#define  IVE_TOP_REG_FRAME_DONE_BGM_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_BGU   0x90
#define  IVE_TOP_REG_FRAME_DONE_BGU_OFFSET 11
#define  IVE_TOP_REG_FRAME_DONE_BGU_MASK   0x800
#define  IVE_TOP_REG_FRAME_DONE_BGU_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_R2Y4   0x90
#define  IVE_TOP_REG_FRAME_DONE_R2Y4_OFFSET 12
#define  IVE_TOP_REG_FRAME_DONE_R2Y4_MASK   0x1000
#define  IVE_TOP_REG_FRAME_DONE_R2Y4_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_BG   0x90
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_BG_OFFSET 13
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_BG_MASK   0x2000
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_BG_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_FG   0x90
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_FG_OFFSET 14
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_FG_MASK   0x4000
#define  IVE_TOP_REG_FRAME_DONE_FRAME2OP_FG_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_MAP   0x90
#define  IVE_TOP_REG_FRAME_DONE_MAP_OFFSET 15
#define  IVE_TOP_REG_FRAME_DONE_MAP_MASK   0x8000
#define  IVE_TOP_REG_FRAME_DONE_MAP_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_THRESH16RO8   0x90
#define  IVE_TOP_REG_FRAME_DONE_THRESH16RO8_OFFSET 16
#define  IVE_TOP_REG_FRAME_DONE_THRESH16RO8_MASK   0x10000
#define  IVE_TOP_REG_FRAME_DONE_THRESH16RO8_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_THRESH   0x90
#define  IVE_TOP_REG_FRAME_DONE_THRESH_OFFSET 17
#define  IVE_TOP_REG_FRAME_DONE_THRESH_MASK   0x20000
#define  IVE_TOP_REG_FRAME_DONE_THRESH_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_ODMA   0x90
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_ODMA_OFFSET 18
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_ODMA_MASK   0x40000
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_ODMA_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_Y   0x90
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_Y_OFFSET 19
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_Y_MASK   0x80000
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_Y_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_C   0x90
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_C_OFFSET 20
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_C_MASK   0x100000
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_C_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_DMAF   0x90
#define  IVE_TOP_REG_FRAME_DONE_DMAF_OFFSET 21
#define  IVE_TOP_REG_FRAME_DONE_DMAF_MASK   0x200000
#define  IVE_TOP_REG_FRAME_DONE_DMAF_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_CCL   0x90
#define  IVE_TOP_REG_FRAME_DONE_CCL_OFFSET 22
#define  IVE_TOP_REG_FRAME_DONE_CCL_MASK   0x400000
#define  IVE_TOP_REG_FRAME_DONE_CCL_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_LK   0x90
#define  IVE_TOP_REG_FRAME_DONE_LK_OFFSET 23
#define  IVE_TOP_REG_FRAME_DONE_LK_MASK   0x800000
#define  IVE_TOP_REG_FRAME_DONE_LK_BITS   0x1
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_YC   0x90
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_YC_OFFSET 24
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_YC_MASK   0x1000000
#define  IVE_TOP_REG_FRAME_DONE_FILTEROP_WDMA_YC_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_HIST   0x94
#define  IVE_TOP_REG_INTR_EN_HIST_OFFSET 0
#define  IVE_TOP_REG_INTR_EN_HIST_MASK   0x1
#define  IVE_TOP_REG_INTR_EN_HIST_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_INTG   0x94
#define  IVE_TOP_REG_INTR_EN_INTG_OFFSET 1
#define  IVE_TOP_REG_INTR_EN_INTG_MASK   0x2
#define  IVE_TOP_REG_INTR_EN_INTG_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_SAD   0x94
#define  IVE_TOP_REG_INTR_EN_SAD_OFFSET 2
#define  IVE_TOP_REG_INTR_EN_SAD_MASK   0x4
#define  IVE_TOP_REG_INTR_EN_SAD_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_NCC   0x94
#define  IVE_TOP_REG_INTR_EN_NCC_OFFSET 3
#define  IVE_TOP_REG_INTR_EN_NCC_MASK   0x8
#define  IVE_TOP_REG_INTR_EN_NCC_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_FILTEROP_ODMA   0x94
#define  IVE_TOP_REG_INTR_EN_FILTEROP_ODMA_OFFSET 4
#define  IVE_TOP_REG_INTR_EN_FILTEROP_ODMA_MASK   0x10
#define  IVE_TOP_REG_INTR_EN_FILTEROP_ODMA_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_Y   0x94
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_Y_OFFSET 5
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_Y_MASK   0x20
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_Y_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_C   0x94
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_C_OFFSET 6
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_C_MASK   0x40
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_C_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_DMAF   0x94
#define  IVE_TOP_REG_INTR_EN_DMAF_OFFSET 7
#define  IVE_TOP_REG_INTR_EN_DMAF_MASK   0x80
#define  IVE_TOP_REG_INTR_EN_DMAF_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_CCL   0x94
#define  IVE_TOP_REG_INTR_EN_CCL_OFFSET 8
#define  IVE_TOP_REG_INTR_EN_CCL_MASK   0x100
#define  IVE_TOP_REG_INTR_EN_CCL_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_LK   0x94
#define  IVE_TOP_REG_INTR_EN_LK_OFFSET 9
#define  IVE_TOP_REG_INTR_EN_LK_MASK   0x200
#define  IVE_TOP_REG_INTR_EN_LK_BITS   0x1
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_YC   0x94
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_YC_OFFSET 10
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_YC_MASK   0x400
#define  IVE_TOP_REG_INTR_EN_FILTEROP_WDMA_YC_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_HIST   0x98
#define  IVE_TOP_REG_INTR_STATUS_HIST_OFFSET 0
#define  IVE_TOP_REG_INTR_STATUS_HIST_MASK   0x1
#define  IVE_TOP_REG_INTR_STATUS_HIST_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_INTG   0x98
#define  IVE_TOP_REG_INTR_STATUS_INTG_OFFSET 1
#define  IVE_TOP_REG_INTR_STATUS_INTG_MASK   0x2
#define  IVE_TOP_REG_INTR_STATUS_INTG_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_SAD   0x98
#define  IVE_TOP_REG_INTR_STATUS_SAD_OFFSET 2
#define  IVE_TOP_REG_INTR_STATUS_SAD_MASK   0x4
#define  IVE_TOP_REG_INTR_STATUS_SAD_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_NCC   0x98
#define  IVE_TOP_REG_INTR_STATUS_NCC_OFFSET 3
#define  IVE_TOP_REG_INTR_STATUS_NCC_MASK   0x8
#define  IVE_TOP_REG_INTR_STATUS_NCC_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_ODMA   0x98
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_ODMA_OFFSET 4
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_ODMA_MASK   0x10
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_ODMA_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_Y   0x98
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_Y_OFFSET 5
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_Y_MASK   0x20
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_Y_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_C   0x98
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_C_OFFSET 6
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_C_MASK   0x40
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_C_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_DMAF   0x98
#define  IVE_TOP_REG_INTR_STATUS_DMAF_OFFSET 7
#define  IVE_TOP_REG_INTR_STATUS_DMAF_MASK   0x80
#define  IVE_TOP_REG_INTR_STATUS_DMAF_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_CCL   0x98
#define  IVE_TOP_REG_INTR_STATUS_CCL_OFFSET 8
#define  IVE_TOP_REG_INTR_STATUS_CCL_MASK   0x100
#define  IVE_TOP_REG_INTR_STATUS_CCL_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_LK   0x98
#define  IVE_TOP_REG_INTR_STATUS_LK_OFFSET 9
#define  IVE_TOP_REG_INTR_STATUS_LK_MASK   0x200
#define  IVE_TOP_REG_INTR_STATUS_LK_BITS   0x1
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_YC   0x98
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_YC_OFFSET 10
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_YC_MASK   0x400
#define  IVE_TOP_REG_INTR_STATUS_FILTEROP_WDMA_YC_BITS   0x1
#define  IVE_TOP_REG_RESIZE_SRC_WD   0x100
#define  IVE_TOP_REG_RESIZE_SRC_WD_OFFSET 0
#define  IVE_TOP_REG_RESIZE_SRC_WD_MASK   0xffff
#define  IVE_TOP_REG_RESIZE_SRC_WD_BITS   0x10
#define  IVE_TOP_REG_RESIZE_SRC_HT   0x100
#define  IVE_TOP_REG_RESIZE_SRC_HT_OFFSET 16
#define  IVE_TOP_REG_RESIZE_SRC_HT_MASK   0xffff0000
#define  IVE_TOP_REG_RESIZE_SRC_HT_BITS   0x10
#define  IVE_TOP_REG_RESIZE_DST_WD   0x104
#define  IVE_TOP_REG_RESIZE_DST_WD_OFFSET 0
#define  IVE_TOP_REG_RESIZE_DST_WD_MASK   0xffff
#define  IVE_TOP_REG_RESIZE_DST_WD_BITS   0x10
#define  IVE_TOP_REG_RESIZE_DST_HT   0x104
#define  IVE_TOP_REG_RESIZE_DST_HT_OFFSET 16
#define  IVE_TOP_REG_RESIZE_DST_HT_MASK   0xffff0000
#define  IVE_TOP_REG_RESIZE_DST_HT_BITS   0x10
#define  IVE_TOP_REG_RESIZE_H_SC_FAC   0x108
#define  IVE_TOP_REG_RESIZE_H_SC_FAC_OFFSET 0
#define  IVE_TOP_REG_RESIZE_H_SC_FAC_MASK   0x3ffff
#define  IVE_TOP_REG_RESIZE_H_SC_FAC_BITS   0x12
#define  IVE_TOP_REG_RESIZE_V_SC_FAC   0x10c
#define  IVE_TOP_REG_RESIZE_V_SC_FAC_OFFSET 0
#define  IVE_TOP_REG_RESIZE_V_SC_FAC_MASK   0x3ffff
#define  IVE_TOP_REG_RESIZE_V_SC_FAC_BITS   0x12
#define  IVE_TOP_REG_RESIZE_H_INI_PH   0x110
#define  IVE_TOP_REG_RESIZE_H_INI_PH_OFFSET 0
#define  IVE_TOP_REG_RESIZE_H_INI_PH_MASK   0x1fff
#define  IVE_TOP_REG_RESIZE_H_INI_PH_BITS   0xd
#define  IVE_TOP_REG_RESIZE_V_INI_PH   0x110
#define  IVE_TOP_REG_RESIZE_V_INI_PH_OFFSET 16
#define  IVE_TOP_REG_RESIZE_V_INI_PH_MASK   0x1fff0000
#define  IVE_TOP_REG_RESIZE_V_INI_PH_BITS   0xd
#define  IVE_TOP_REG_RESIZE_H_NOR   0x114
#define  IVE_TOP_REG_RESIZE_H_NOR_OFFSET 0
#define  IVE_TOP_REG_RESIZE_H_NOR_MASK   0xffff
#define  IVE_TOP_REG_RESIZE_H_NOR_BITS   0x10
#define  IVE_TOP_REG_RESIZE_V_NOR   0x114
#define  IVE_TOP_REG_RESIZE_V_NOR_OFFSET 16
#define  IVE_TOP_REG_RESIZE_V_NOR_MASK   0xffff0000
#define  IVE_TOP_REG_RESIZE_V_NOR_BITS   0x10
#define  IVE_TOP_REG_RESIZE_IP_EN   0x118
#define  IVE_TOP_REG_RESIZE_IP_EN_OFFSET 0
#define  IVE_TOP_REG_RESIZE_IP_EN_MASK   0x1
#define  IVE_TOP_REG_RESIZE_IP_EN_BITS   0x1
#define  IVE_TOP_REG_RESIZE_DBG_EN   0x118
#define  IVE_TOP_REG_RESIZE_DBG_EN_OFFSET 1
#define  IVE_TOP_REG_RESIZE_DBG_EN_MASK   0x2
#define  IVE_TOP_REG_RESIZE_DBG_EN_BITS   0x1
#define  IVE_TOP_REG_RESIZE_AREA_FAST   0x118
#define  IVE_TOP_REG_RESIZE_AREA_FAST_OFFSET 2
#define  IVE_TOP_REG_RESIZE_AREA_FAST_MASK   0x4
#define  IVE_TOP_REG_RESIZE_AREA_FAST_BITS   0x1
#define  IVE_TOP_REG_RESIZE_BLNR_MODE   0x118
#define  IVE_TOP_REG_RESIZE_BLNR_MODE_OFFSET 3
#define  IVE_TOP_REG_RESIZE_BLNR_MODE_MASK   0x8
#define  IVE_TOP_REG_RESIZE_BLNR_MODE_BITS   0x1
#define  IVE_TOP_REG_RESIZE_SC_DBG_H1   0x11c
#define  IVE_TOP_REG_RESIZE_SC_DBG_H1_OFFSET 0
#define  IVE_TOP_REG_RESIZE_SC_DBG_H1_MASK   0xffffffff
#define  IVE_TOP_REG_RESIZE_SC_DBG_H1_BITS   0x20
#define  IVE_TOP_REG_RESIZE_SC_DBG_H2   0x120
#define  IVE_TOP_REG_RESIZE_SC_DBG_H2_OFFSET 0
#define  IVE_TOP_REG_RESIZE_SC_DBG_H2_MASK   0xffffffff
#define  IVE_TOP_REG_RESIZE_SC_DBG_H2_BITS   0x20
#define  IVE_TOP_REG_RESIZE_SC_DBG_V1   0x124
#define  IVE_TOP_REG_RESIZE_SC_DBG_V1_OFFSET 0
#define  IVE_TOP_REG_RESIZE_SC_DBG_V1_MASK   0xffffffff
#define  IVE_TOP_REG_RESIZE_SC_DBG_V1_BITS   0x20
#define  IVE_TOP_REG_RESIZE_SC_DBG_V2   0x128
#define  IVE_TOP_REG_RESIZE_SC_DBG_V2_OFFSET 0
#define  IVE_TOP_REG_RESIZE_SC_DBG_V2_MASK   0xffffffff
#define  IVE_TOP_REG_RESIZE_SC_DBG_V2_BITS   0x20
#define  IVE_TOP_REG_THRESH_TOP_MOD   0x130
#define  IVE_TOP_REG_THRESH_TOP_MOD_OFFSET 0
#define  IVE_TOP_REG_THRESH_TOP_MOD_MASK   0x3
#define  IVE_TOP_REG_THRESH_TOP_MOD_BITS   0x2
#define  IVE_TOP_REG_THRESH_THRESH_EN   0x130
#define  IVE_TOP_REG_THRESH_THRESH_EN_OFFSET 4
#define  IVE_TOP_REG_THRESH_THRESH_EN_MASK   0x10
#define  IVE_TOP_REG_THRESH_THRESH_EN_BITS   0x1
#define  IVE_TOP_REG_THRESH_SOFTRST   0x130
#define  IVE_TOP_REG_THRESH_SOFTRST_OFFSET 8
#define  IVE_TOP_REG_THRESH_SOFTRST_MASK   0x100
#define  IVE_TOP_REG_THRESH_SOFTRST_BITS   0x1
#define  IVE_TOP_REG_THRESH_16TO8_MOD   0x134
#define  IVE_TOP_REG_THRESH_16TO8_MOD_OFFSET 0
#define  IVE_TOP_REG_THRESH_16TO8_MOD_MASK   0x7
#define  IVE_TOP_REG_THRESH_16TO8_MOD_BITS   0x3
#define  IVE_TOP_REG_THRESH_16TO8_S8BIAS   0x134
#define  IVE_TOP_REG_THRESH_16TO8_S8BIAS_OFFSET 8
#define  IVE_TOP_REG_THRESH_16TO8_S8BIAS_MASK   0xff00
#define  IVE_TOP_REG_THRESH_16TO8_S8BIAS_BITS   0x8
#define  IVE_TOP_REG_THRESH_16TO8_U8NUM_DIV_U16DEN   0x134
#define  IVE_TOP_REG_THRESH_16TO8_U8NUM_DIV_U16DEN_OFFSET 16
#define  IVE_TOP_REG_THRESH_16TO8_U8NUM_DIV_U16DEN_MASK   0xffff0000
#define  IVE_TOP_REG_THRESH_16TO8_U8NUM_DIV_U16DEN_BITS   0x10
#define  IVE_TOP_REG_THRESH_ST_16TO8_EN   0x138
#define  IVE_TOP_REG_THRESH_ST_16TO8_EN_OFFSET 0
#define  IVE_TOP_REG_THRESH_ST_16TO8_EN_MASK   0x1
#define  IVE_TOP_REG_THRESH_ST_16TO8_EN_BITS   0x1
#define  IVE_TOP_REG_THRESH_ST_16TO8_U8NUMERATOR   0x138
#define  IVE_TOP_REG_THRESH_ST_16TO8_U8NUMERATOR_OFFSET 8
#define  IVE_TOP_REG_THRESH_ST_16TO8_U8NUMERATOR_MASK   0xff00
#define  IVE_TOP_REG_THRESH_ST_16TO8_U8NUMERATOR_BITS   0x8
#define  IVE_TOP_REG_THRESH_ST_16TO8_MAXEIGVAL   0x138
#define  IVE_TOP_REG_THRESH_ST_16TO8_MAXEIGVAL_OFFSET 16
#define  IVE_TOP_REG_THRESH_ST_16TO8_MAXEIGVAL_MASK   0xffff0000
#define  IVE_TOP_REG_THRESH_ST_16TO8_MAXEIGVAL_BITS   0x10
#define  IVE_TOP_REG_THRESH_S16_ENMODE   0x13c
#define  IVE_TOP_REG_THRESH_S16_ENMODE_OFFSET 0
#define  IVE_TOP_REG_THRESH_S16_ENMODE_MASK   0x3
#define  IVE_TOP_REG_THRESH_S16_ENMODE_BITS   0x2
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MIN   0x13c
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MIN_OFFSET 8
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MIN_MASK   0xff00
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MIN_BITS   0x8
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MID   0x13c
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MID_OFFSET 16
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MID_MASK   0xff0000
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MID_BITS   0x8
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MAX   0x13c
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MAX_OFFSET 24
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MAX_MASK   0xff000000
#define  IVE_TOP_REG_THRESH_S16_U8BIT_MAX_BITS   0x8
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_L   0x140
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_L_OFFSET 0
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_L_MASK   0xffff
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_L_BITS   0x10
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_H   0x140
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_H_OFFSET 16
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_H_MASK   0xffff0000
#define  IVE_TOP_REG_THRESH_S16_BIT_THR_H_BITS   0x10
#define  IVE_TOP_REG_THRESH_U16_ENMODE   0x144
#define  IVE_TOP_REG_THRESH_U16_ENMODE_OFFSET 0
#define  IVE_TOP_REG_THRESH_U16_ENMODE_MASK   0x1
#define  IVE_TOP_REG_THRESH_U16_ENMODE_BITS   0x1
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MIN   0x144
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MIN_OFFSET 8
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MIN_MASK   0xff00
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MIN_BITS   0x8
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MID   0x144
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MID_OFFSET 16
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MID_MASK   0xff0000
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MID_BITS   0x8
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MAX   0x144
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MAX_OFFSET 24
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MAX_MASK   0xff000000
#define  IVE_TOP_REG_THRESH_U16_U8BIT_MAX_BITS   0x8
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_L   0x148
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_L_OFFSET 0
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_L_MASK   0xffff
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_L_BITS   0x10
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_H   0x148
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_H_OFFSET 16
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_H_MASK   0xffff0000
#define  IVE_TOP_REG_THRESH_U16_BIT_THR_H_BITS   0x10
#define  IVE_TOP_REG_THRESH_U8BIT_THR_L   0x14c
#define  IVE_TOP_REG_THRESH_U8BIT_THR_L_OFFSET 0
#define  IVE_TOP_REG_THRESH_U8BIT_THR_L_MASK   0xff
#define  IVE_TOP_REG_THRESH_U8BIT_THR_L_BITS   0x8
#define  IVE_TOP_REG_THRESH_U8BIT_THR_H   0x14c
#define  IVE_TOP_REG_THRESH_U8BIT_THR_H_OFFSET 8
#define  IVE_TOP_REG_THRESH_U8BIT_THR_H_MASK   0xff00
#define  IVE_TOP_REG_THRESH_U8BIT_THR_H_BITS   0x8
#define  IVE_TOP_REG_THRESH_ENMODE   0x14c
#define  IVE_TOP_REG_THRESH_ENMODE_OFFSET 16
#define  IVE_TOP_REG_THRESH_ENMODE_MASK   0x70000
#define  IVE_TOP_REG_THRESH_ENMODE_BITS   0x3
#define  IVE_TOP_REG_THRESH_U8BIT_MIN   0x150
#define  IVE_TOP_REG_THRESH_U8BIT_MIN_OFFSET 0
#define  IVE_TOP_REG_THRESH_U8BIT_MIN_MASK   0xff
#define  IVE_TOP_REG_THRESH_U8BIT_MIN_BITS   0x8
#define  IVE_TOP_REG_THRESH_U8BIT_MID   0x150
#define  IVE_TOP_REG_THRESH_U8BIT_MID_OFFSET 8
#define  IVE_TOP_REG_THRESH_U8BIT_MID_MASK   0xff00
#define  IVE_TOP_REG_THRESH_U8BIT_MID_BITS   0x8
#define  IVE_TOP_REG_THRESH_U8BIT_MAX   0x150
#define  IVE_TOP_REG_THRESH_U8BIT_MAX_OFFSET 16
#define  IVE_TOP_REG_THRESH_U8BIT_MAX_MASK   0xff0000
#define  IVE_TOP_REG_THRESH_U8BIT_MAX_BITS   0x8
#define  IVE_TOP_REG_NCC_NEMERATOR_L   0x160
#define  IVE_TOP_REG_NCC_NEMERATOR_L_OFFSET 0
#define  IVE_TOP_REG_NCC_NEMERATOR_L_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_NEMERATOR_L_BITS   0x20
#define  IVE_TOP_REG_NCC_NEMERATOR_M   0x164
#define  IVE_TOP_REG_NCC_NEMERATOR_M_OFFSET 0
#define  IVE_TOP_REG_NCC_NEMERATOR_M_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_NEMERATOR_M_BITS   0x20
#define  IVE_TOP_REG_NCC_QUADSUM0_L   0x168
#define  IVE_TOP_REG_NCC_QUADSUM0_L_OFFSET 0
#define  IVE_TOP_REG_NCC_QUADSUM0_L_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_QUADSUM0_L_BITS   0x20
#define  IVE_TOP_REG_NCC_QUADSUM0_M   0x16c
#define  IVE_TOP_REG_NCC_QUADSUM0_M_OFFSET 0
#define  IVE_TOP_REG_NCC_QUADSUM0_M_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_QUADSUM0_M_BITS   0x20
#define  IVE_TOP_REG_NCC_QUADSUM1_L   0x170
#define  IVE_TOP_REG_NCC_QUADSUM1_L_OFFSET 0
#define  IVE_TOP_REG_NCC_QUADSUM1_L_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_QUADSUM1_L_BITS   0x20
#define  IVE_TOP_REG_NCC_QUADSUM1_M   0x174
#define  IVE_TOP_REG_NCC_QUADSUM1_M_OFFSET 0
#define  IVE_TOP_REG_NCC_QUADSUM1_M_MASK   0xffffffff
#define  IVE_TOP_REG_NCC_QUADSUM1_M_BITS   0x20
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_0   0x180
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_0_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_0_MASK   0xfff
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_0_BITS   0xc
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_1   0x180
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_1_OFFSET 16
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_1_MASK   0x7fff0000
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_1_BITS   0xf
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_UPDATE   0x184
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_UPDATE_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_UPDATE_MASK   0x1
#define  IVE_TOP_REG_CSC_R2Y4_TAB_SW_UPDATE_BITS   0x1
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_UPDATE   0x184
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_UPDATE_OFFSET 16
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_UPDATE_MASK   0x10000
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_UPDATE_BITS   0x1
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_00   0x188
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_00_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_00_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_00_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_01   0x18c
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_01_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_01_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_01_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_02   0x190
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_02_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_02_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_02_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_03   0x194
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_03_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_03_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_03_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_04   0x198
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_04_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_04_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_04_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_05   0x19c
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_05_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_05_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_05_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_06   0x1a0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_06_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_06_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_06_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_07   0x1a4
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_07_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_07_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_07_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_08   0x1a8
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_08_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_08_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_08_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_09   0x1ac
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_09_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_09_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_09_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_10   0x1b0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_10_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_10_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_10_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_11   0x1b4
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_11_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_11_MASK   0x7ffff
#define  IVE_TOP_REG_CSC_R2Y4_COEFF_SW_11_BITS   0x13
#define  IVE_TOP_REG_CSC_R2Y4_ENMODE   0x1bc
#define  IVE_TOP_REG_CSC_R2Y4_ENMODE_OFFSET 0
#define  IVE_TOP_REG_CSC_R2Y4_ENMODE_MASK   0xf
#define  IVE_TOP_REG_CSC_R2Y4_ENMODE_BITS   0x4
#define  IVE_TOP_REG_CSC_R2Y4_ENABLE   0x1bc
#define  IVE_TOP_REG_CSC_R2Y4_ENABLE_OFFSET 4
#define  IVE_TOP_REG_CSC_R2Y4_ENABLE_MASK   0x10
#define  IVE_TOP_REG_CSC_R2Y4_ENABLE_BITS   0x1
